1. Field of the Invention
The present invention relates to a memory device having a hierarchical bit line for lessening the size of a chip, and more particularly to a memory device having a hierarchical bit line structure of which a global bit line can be divided into two parts.
2. Description of Prior Art
In general, one of the most important factors in the memory devices is the price. Therefore, the method to increase an yield and adopt an economical manufacturing process can be used. In addition, the way of increasing the namer of dies, which are integrated within the chips, is available. As usual, the size of the die can be lessened by means of scaling down the design rule which is applied to the design of the memory device with an advanced process.
The area or cells and sense amplifiers occupy a large proportion of the VLSI memory device. In a highly integrated memory device, the number of the cells connected to the bit line keeps constant, which comes from the fact that the ratio of the bit line capacitance and the cell capacitance should be low for a stable read operation of the memory cell.
Thus, the number of the sense amplifiers increases in proportion to the higher integration of the memory. Therefore, the size of the die can be diminished by decreasing the number of the sense amplifier.
As mentioned above, the bit line having a hierarchy can be adopted for the method of decreasing the number of the sense amplifier.
FIG. 1A shows a hierarchical bit line in accordance with a prior art.
The bit line connected to the cells has m(a natural number) sub bit line/lines SBi and /SBi(/SBi is an inverted signal of SBi) (1&lt;i&lt;m), respectively, which are connected to the global bit line GB and /GB by a transistor 4 used as a switch.
In addition, the numeral 1 is a word line, 2 is a cell, 3 is a control signal line for connecting the sub bit line to the global bit line, 5 is a sense amplifier, and 10 is a switching part used for connecting the sub bit line to the global bit line.
FIG. 1B illustrates the operation of the prior hierarchical bit line.
In case of the access to the cell for read and write operation, only the sub bit line SB2 and /SB2 connected to the cell 2 is connected to the global bit line GB and /GB, and the rest of the sub bit lines are separated so that the total capacitance of the bit line, and the total number of the sense amplifiers can be decreased.
FIG. 2A shows the area of the cell array 100 and the area of the sense amplifier 110 of the prior art.
FIG. 2B shows the area of the cell array 120, 130, and the area of the sense amplifier array 110, and the area of the switching part array 140 when a hierarchical bit line is applied.
In the hierarchical bit line of FIG. 2B, compared with the prior hierarchical bit line, it is noted that in case the number of the cell connected to the global bit line is increased as many as 4 times, the area is decreased by the difference between the area of 3 sense amplifier arrays 110 and the area of the switching part array 140.
In general, the resistance and the capacitance of the sub bit line are high, because it uses tungsten-polycide (W-polycide) consisting of polysilicon layer and tungsten silicide layer. However, the resistance and the capacitance of the global bit line are low, because a metal layer is used.
Therefore, when the prior hierarchical bit line is applied to the memory product, the major drawback is that it is difficult to acquire an easy manufacturing process and a high yield because a width and a gap of the global bit line should be set in a minimum feature size.